With the shrinking of the critical dimension of semiconductor device, the contact resistance of semiconductor device such as MOS field effect transistor to the upper layer interconnect impacts the device's performance more seriously. A conventional method for reducing the contact resistance is to form metal silicide on the contact electrode of the device.
FIGS. 1-3 schematically show a method for forming metal silicide in prior art step by step, taking a MOS field effect transistor for example.
Referring to FIG. 1, a semiconductor substrate 10 is provided. A MOS field effect transistor is formed on the semiconductor substrate 10 which comprises a gate stack 11, a source region 12 in the semiconductor on one side of the gate stack 11, and a drain region 13 in the semiconductor substrate 10 on the other side of the gate stack 11. The gate stack 11 comprises a gate dielectric layer 11a, a gate electrode 11b, and a spacer 11c around the gate dielectric layer 11a and the gate electrode 11b. The gate dielectric layer 11a is generally formed of silicon oxide. The gate electrode 11b is generally formed of polycrystalline silicon. The spacer 11c is generally formed of silicon oxide, silicon nitride or a combination thereof. Afterwards, a metal layer 14 is deposited for covering the semiconductor 10 and the gate stack 11. In order to reduce the formation temperature and produce the metal silicide with lower resistivity, the material of the metal layer 14 is generally Ni-based metals such as Ni, Ni—Pt alloy and so on, so that Ni-based silicide (such as NiSi, NiPtSi, NiCoSi, NiPtCoSi and so on) is produced.
Referring to FIG. 2, a thermal treatment, such as annealing, is performed on the semiconductor substrate 10. The metal layer 14 reacts with the silicon on the surface of the source region 12 and the drain region 13, and the polycrystalline silicon on the surface of the gate electrode 11b, producing metal silicide 14a with low resistivity. The spacer 11c is formed of dielectric material and does not react with the metal layer 14.
Referring to FIG. 3, the part of the metal layer 14, which does not react with the semiconductor substrate 10, is removed. The formation process of metal silicide finishes.
Still referring to FIG. 2 and FIG. 3, during the formation process of the metal silicide 14a, excess metal material of the metal layer 14 on the spacer 11c and the part of the metal layer 14 which does not react with the semiconductor substrate 10 would diffuse laterally, such that the metal silicide 14a on the source region 12 and the drain region 13 encroaches into the region 15 under the spacer 11c, or even into the semiconductor substrate 10 under the gate dielectric layer 11a, which is the channel region of the MOS field effect transistor. It leads to larger gate electrode leakage current, lower reliability and even a short between the source region 12 and the drain region 13, degrading the device performance seriously. As for a MOS field effect transistor formed on a SOI (Silicon On Insulator), because the silicon source itself in the source or drain regions is very limited, the lateral encroachment of metal silicide into the channel is even aggravating.